1. Field of the Invention
The present invention relates to an apparatus for receiving and transmitting asynchronous serial data (referred to as “UART” (Universal Asynchronous Receiver Transmitter)).
2. Description of the Related Art
Referring to FIG. 9 of the accompanying drawings, a general structure of a conventional UART is illustrated. The UART includes a baudrate generator 1, a shift register 2, a switch 3 for switching between transmission and reception, and a UART controller 4. The UART is controlled by signals and data supplied from a data bus 5.
The baudrate generator 1 includes a register 1a to store a transfer rate set value, a baudrate counter (reload counter) 1b for loading the transfer rate set value to count a time corresponding to a half of one bit width of outgoing data, and a flip-flop 1c for receiving a carry signal from the baudrate counter 1b and supplying a shift clock S1 to the shift register 2.
A reference clock CLK which is utilized to determine the transfer rate is counted by the baudrate generator 1 such that the shift clock S1 having a period equal to the bit width is generated. The shift clock S1 is used by the shift register 2 to shift a transmission bit or reception bit in order to perform transmission and reception of serial data. Switching between transmission and reception is effected by the switch 3 under the control of the UART controller 4. Entry of the transfer rate set value, preparation of the outgoing data and retrieval of received data (incoming data) is performed through the data bus 5.
When a frequency of the reference clock is 4.9152 MHz and data should be transmitted at a transfer rate of 9600 bps, then the value in the register 1a is determined such that the baudrate counter 1b produces a carry signal every time the baudrate counter 1b counts the reference clock CLK 256 times. The flip-flop 1c supplies the shift clock S1 to the shift register 2 at intervals equal to 512 reference clocks. Thus, it is possible to send data at the data transfer rate of 9600 bps (4.9152×106/512=9600 bps).
FIG. 10 of the accompanying drawings illustrates an example when one bit width corresponds to eight reference clocks. The register 1a stores “FCh” such that the baudrate counter 1b outputs a carry signal every time the baudrate counter 1b counts the reference clock CLK four times. It should be noted that a baudrate counter value in the timing chart shown in FIG. 10 includes a value of the flip-flop 1c. 
When the UART transfers data at a rate of 9600 bps with the reference clock frequency being 3.58 MHz (e.g., when an IC card is used), one bit time becomes 372.9166 . . . (3.58×106/9600=372.9166 . . . ) and the transfer rate set value becomes 186.4583 . . . . In this case, an approximate value 186 is used as the transfer rate set value so that the transfer rate contains an error. In reality, however, since the transfer rate (9600 bps) is slow, the error would cause substantially no problem. In general, substantially no problem would occur as long as the time from the start bit to the n'th bit falls within n±0.2 bit time. When the transfer rate is fast, such as 38.4 kbps, 76.8 kbps and 372 kbps, a significant gap will appear between a theoretical transfer rate set value and an actual transfer rate set value. High speed data transfer cannot be performed unless a frequency of the reference clock is increased to reduce the error.